1. Field of the Invention
The present invention relates to a coding apparatus for carrying out serial concatenated trellis coded modulation, a coding method and a recording medium having a coded program recorded therein, and a decoding apparatus for decoding data subjected to serial concatenated trellis coded modulation, a decoding method and a recording medium having a decoded program recorded therein.
2. Description of Related Art
Lately, the study on, for example, a communication field such as a mobile communication and a deep space communication, a broadcasting field such as terrestrial wave or satellite digital broadcasting, and a magnetic, light or photo-electro recording field has been progressed materially, but with this, the study on a code theory for the purpose of making error correction coding and decoding efficient has been carried out actively.
As a theoretical limit of code performance, a Shannon limit implied by a so-called Shannon's channel coding theorem is known.
As the coding method indicative of the performance close to the Shannon limit, there is known a coding method by serially concatenated convolutional codes described in, for example, [S. Benedetto, G. Montorsi, D. Divsalar, F. Pollara, “Serial Concatenation of Interleaved Codes: Performance Analysis, Design, and Iterative Decoding”, TDA Progress 42-126, Jet Propulsion Laboratory, Pasadena, Calif., Aug. 15, 1996].
The coding by the serially concatenated convolutional codes is carried out by an apparatus having two convolutional coders and an interleaver serially concatenated. The decoding by the serially concatenated convolutional codes is carried out by an apparatus having two decoding circuits for outputting a soft-output serially concatenated, and information is transferred between the two decoding circuits to obtain the final decoded result.
Further, as an application of the coding by the serially concatenated convolutional codes, there is also known a serial concatenated trellis coded modulation, which is hereinafter referred to as SCTCM, described in, for example, [D. Divsalar, F. Pollars, “Serial and Hybrid Concatenation Codes with Applications”, in Proc., Int. Symp. On Turbo Codes and Related Topics, Brest, France, pp. 80-87, September 1997]. The SCTCM system comprises a combination of the coding by the serially concatenated convolutional codes and a multi-value modulation, which collectively considers an arrangement of a signal point of a modulation signal and the decoding feature of an error correction code.
The coding apparatus for carrying out coding according to th SCTCM system and the decoding apparatus for carrying out decoding according to th SCTCM system will be described hereinafter. In the following description, a contemplation is made of a case in which as shown in FIG. 1, digital information is subjected to serially concatenated convolutional coding by a coder 201 provided on a transmission device not shown, which output is input into a receiving apparatus not shown through a memoryless channel 202 with noises, which is decoded by a decoder 203 provided on the receiving apparatus.
As the coding apparatus 201 for carrying out coding according to th SCTCM system, there has been proposed an apparatus comprising a convolutional coder 210 for carrying out coding of a first code (hereinafter referred to as an outer code), an interleaver 220 for rearranging order of data input, a convolutional coder 230 for carrying out coding of a second code (hereinafter referred to as an inner code), a multi-value modulation mapping circuit 240 for carrying out mapping of a signal point on the basis of a predetermined modulation system, and a demultiplexer 250 for demultiplexing an output from the multi-value modulation mapping circuit 240, as shown in FIG. 2. The coding apparatus 201 carries out serially concatenated convolutional operation whose code rate is “4/6=2/3” with respect to input data D201 of 4-bit input, which is converted to coded data D204 of 6-bit and subjected to mapping to, for example, a transmission symbol of a 8 PSK (8-Phase Shift Keying) modulation system to obtain two transmission symbols D205 of 3 bits, which are output as a coded transmission symbol D206 one by one.
The convolutional coder 210 comprises, as shown in FIG. 3, three shift registers 211, 212, 213, and five exclusive OR circuits 214, 215, 216, 217, 218.
The shift register 211 continues to supply data of 1 bit being held to the exclusive OR circuits 214, 215, 216, 217. The shift register 211 is synchronized with a clock to newly hold an input data D2011 of 1 bit out of input data D201 of 4 bits, and newly supplies the input data 2011 to the exclusive OR circuits 214, 215, 216, 217.
The shift register 212 continues to supply data of 1 bit being held to the exclusive OR circuits 217, 218. The shift register 212 is synchronized with a clock to newly hold an input data D2012 of 1 bit out of input data D201 of 4 bits, and newly supplies the input data 2012 to the exclusive OR circuits 217, 218.
The shift register 213 continues to supply data of 1 bit being held to the exclusive OR circuits 214, 215. The shift register 213 is synchronized with a clock to newly hold an input data D2013 of 1 bit out of input data D201 of 4 bits, and newly supplies the input data D2013 to the exclusive OR circuits 214, 215.
The exclusive OR circuit 214 uses data supplied from the shift register 211, data supplied from the shift register 212, data supplied from the shift register 213, an input data D2014 of 1 bit out of input data D201 of 4 bits to carry out exclusive OR operation to output the operation result to the interleaver 220 in the later stage as a coded data D2021 of 1 bit out of coded data D202 of 5 bits.
The exclusive OR circuit 215 uses data supplied from the shift register 211, data supplied from the shift register 213, and an input data D2014 to carry out exclusive OR operation to output the operation result to the interleaver 220 in the later stage as a coded data D2022 of 1 bit out of coded data D202 of 5 bits.
The exclusive OR circuit 216 uses data supplied from the shift register 211, data supplied from the shift register 212, and input data D2013, 2014 to carry out exclusive OR operation to output the operation result to the interleaver 220 in the later stage as a coded data D2023 of 1 bit out of coded data D202 of 5 bits.
The exclusive OR circuit 217 uses data supplied from the shift register 211, and input data D2012, D2013 to carry out exclusive OR operation to output the operation result to the interleaver 220 in the later stage as a coded data D2024 of 1 bit out of coded data D202 of 5 bits.
The exclusive OR circuit 218 uses input data D2011, D2012, D2014 to carry out exclusive OR operation to output the operation result to the interleaver 220 in the later stage as a coded data D2025 of 1 bit out of coded data D202 of 5 bits.
The convolutional coder 210 as described, when input data D2011, D2012, D2013, D2014 of 4 bits are input, carries out convolutional operation with respect to these D2011, D2012, D2013, D2014 and outputs the operation result to an interleaver 220 in the later stage as coded data D2021, D2022, D2023, D2024. That is, the convolutional coder 210 carries out convolutional operation whose code rate is “4/5” as coding of an outer code, and outputs the coded data D202 to the interleaver 220 in the later stage.
The interleaver 220 comprises, as shown in FIG. 4, an input data holding memory 221 for holding data input, a data exchange circuit 222 for carrying out rearrangement (exchange) of order of data input, an exchange data ROM (Read only Memory) 223 for supplying exchange position information of data, and an output data holding memory 224 for holding data output.
The input data holding memory 221 holds coded data D202 comprising five bit series output from the convolutional coder 210 to supply these coded data 202 to the data exchange circuit 222 at a predetermined timing.
The data exchange circuit 222 carries out rearrangement of order of the coded data D202 supplied from the input data holding memory 221 on the basis of exchange position information of data stored in the data exchange circuit 222. The data exchange circuit 222 supplies the rearranged data to the output data holding memory 224.
The exchange data ROM 223 stores, for example, exchange position information of data decided on the basis of random number generated. That is, the interleaver 220 is constituted by a random interleaver for carrying out interleave on the basis of the exchange position information. The exchange position information stored in the exchange data ROM 223 is read out by the data exchange circuit 222 at will.
The output data holding memory 224 holds data supplied from the data exchange circuit 222, and outputs these data to the convolutional coder 230 in the later stage at a predetermined timing as interleave data D203 comprising five bit series.
The interleaver 220 as described applies interleave to the coded data D202 comprising five bit series output from the convolutional coder 210 to output the produced interleave data D203 comprising five bit series to the convolutional coder 230 in the later stage.
The convolutional coder 230 comprises, as shown in FIG. 5, five exclusive OR circuits 231, 232, 233, 234, 235, and one shift register 236.
The exclusive OR circuit 231 uses interleave data D2031, D2032 of 2 bits out of interleave data D203 of 5 bits to carry out exclusive OR operation, and supplies the operation result to the exclusive OR circuit 232.
The exclusive OR circuit 231 uses interleave data D2033 of 1 bit out of interleave data D203 of 5 bits, and data supplied from the exclusive OR circuit 231 to carry out exclusive OR operation, and supplies the operation result to the exclusive OR circuit 233.
The exclusive OR circuit 233 uses interleave data D2034 of 1 bit out of interleave data D203 of 5 bits, and data supplied from the exclusive OR circuit 232 to carry out exclusive OR operation, and supplies the operation result to the exclusive OR circuit 234.
The exclusive OR circuit 234 uses interleave data D2035 of 1 bit out of interleave data D203 of 5 bits, and data supplied from the exclusive OR circuit 233 to carry out exclusive OR operation, and supplies the operation result to the exclusive OR circuit 235, and outputs it the multi-value modulation mapping circuit 240 in the later stage as coded data D2046 of 1 bit out of coded data D204 of 6 bits.
The exclusive OR circuit 235 uses data supplied from the exclusive OR circuit 234, and data supplied from the shift register 236 to carry out exclusive OR operation, and supplies the operation result to the shift register 236, and outputs it the multi-value modulation mapping circuit 240 in the later stage as coded data D2043 of 1 bit out of coded data D204 of 6 bits.
The shift register 236 continues to supply data of 1 bit being held to the exclusive OR circuit 235. The shift register 236 is synchronized with a clock to newly hold data of 1 bit, and newly supplies that data to the exclusive OR circuit 235.
The convolutional coder 230 as described outputs, when interleave data D2031, D2032, D2033, D2034, D2035 are input, the interleave data D2031, D2032, D2033, D2034, D2035 to the multi-value modulation mapping circuit 240 in the later stage as coded data D2041, D2042, D2043, D2044, D2045. The convolutional coder 230 carries out convolutional operation with respect to the interleave data D2031, D2032, D2033, D2034, D2035, and outputs the operation result to the multi-value modulation mapping circuit 240 in the later stage as coded data D2043, D2046. That is, the convolutional coder 230 carries out convolutional operation whose code rate is “5/6” as coding of inner codes to output coded data D204 to the multi-value modulation mapping circuit 240 in the later stage.
The multi-value modulation mapping circuit 240 causes the coded data D204 output from the convolutional coder 230 to synchronize with a clock to apply mapping, for example, to a transmission symbol of the 8 PSK modulation system. Since a signal point of one transmission symbol in the 8 PSK modulation system is data of 3 bits, the multi-value modulation mapping circuit 240 carries out mapping with respect to coded data of 3 bits out of coded data D204 of 6 bits output from the convolutional coder 230 as one transmission symbol to produce two transmission symbols D203. The multi-value modulation mapping circuit 240 outputs the produced transmission symbols D205 to the demultiplexer 250 in the later stage.
The demultiplexer 250 demultipexes two transmission symbols D205 output from the multi-value modulation mapping circuit 240. The demultiplexer 250 is synchronized with a clock of a period of ½ of a clock when the transmission symbol D205 is produced by the multi-value modulation mapping circuit 240 to output to the outside as coded transmission symbols D206 one by one.
The coding apparatus 201 as described carries out convolutional operation whose code rate is “4/5” as coding of outer codes by the convolutional coder 210, and convolutional operation whose code rate is “5/6” as coding of inner codes is carried out by the convolutional coder 230, whereby carrying out serially concatenated convolutional operation whose code rate is “(4/5)×(5×6)=4/6=2/3” as a whole. Data coded and modulated by the coding apparatus 201 are output to the receiving apparatus through the memoryless channel 202.
On the other hand, the decoding apparatus 2 for carrying out decoding of the SCTCM system by the coding apparatus 201 comprises, for example, as shown in FIG. 6, a multiplexer 260 for multiplexing a reception word D207 received, a soft-output decoding circuit 270 for carrying out decoding of inner codes, a deinterleaver 280 for returning order of data input to the original state, an interleaver 290 for rearranging order of data input, and a soft-output decoding circuit 300 for carrying out decoding of outer codes. The decoding apparatus 203 presumes input data D201 in the coding apparatus 201 from the reception word D207 which takes an analog value and which is to be a soft-input due to the influence of noises generated on the memoryless channel 202 to output it as decoded data D213.
The multiplexer 260 outputs two reception words corresponding as one transmission symbol out of reception words D207 of soft-input received by the receiving apparatus to the soft-output decoding circuit 270 in the later stage
The soft-output decoding circuit 270 is provided corresponding to the convolutional coder 230 in the coding apparatus 201 to carry out MAP (Maximum A Posteriori probability) decoding based on the so-called BCJR (Bahl, Cocke, Jelinek and Reviv) algorithm and SOVA (Soft Output Viterbi Algorithm) decoding. The soft-output decoding circuit 270 inputs two reception words D208 of soft-input supplied from the multiplexer 260, inputs priori probability information D209 with respect to information bit of soft-input supplied from the interleaver 290, and uses the reception words D208 and the priori probability information D209 to carry out soft-output decoding of inner codes. The soft-output decoding circuit 270 produces extrinsic information D210 with respect to information bit obtained according to the constraint condition of codes, and outputs the extrinsic information D210 to the deinterleaver 280 in the later stage as a soft-output. It is noted that the extrinsic information D210 corresponds to interleave data D203 interleave by the interleaver 220.
The deinterleaver 280 applies deinterleave to the extrinsic information D210 of soft-input output from the soft-output decoding circuit 270 so that a bit array of interleave data D203 interleaved by the interleaver 220 in the coding apparatus 201 is returned to the original bit array of the coded data D202. The deinterleaver 280 outputs data obtained by deinterleaving as priori probability information D211 with respect to the code bit in the soft-output decoding circuit 300 in the later stage.
The interleaver 290 applies the interleave based on the same exchange position information as the interleaver 220 in the coding apparatus 201 with respect to the extrinsic information 212 with respect to the code bit of soft-input output from the soft-output decoding circuit 300. The interleaver 290 outputs data obtained by interleaving as the priori probability information D209 with respect to the information bit in the soft-output decoding circuit 270.
The soft-output decoding circuit 300 is provided corresponding to the convolutional coder 210 in the coding apparatus 201, and carries out MAP decoding on the basis of the aforementioned BCJR algorithm and SOVA decoding similar to the soft-output decoding circuit 270. The soft-output decoding circuit 300 inputs the priori probability information D211 with respect to the code bit of soft-input output from the deinterleaver 280, inputs priori probability information with respect to the information bit whose value is “0”, though not shown, and uses these priori probability information to carry out soft-output decoding of outer codes. And, the soft-output decoding circuit 300 produces the extrinsic information D212 with respect to the code bit obtained according to the constraint condition of codes, and outputs the extrinsic information D212 to the interleaver 290 as a soft-output. Further, the soft-output decoding circuit 300 produces the extrinsic information with respect to the information bit obtained according to the constraint condition of codes, and outputs decoded data D213 of hard-soft on the basis of the extrinsic information.
The decoding apparatus 203 as described carries out, when the reception word D207 is received, decoding operation from the soft-output decoding circuit 270 to the soft-output decoding circuit 300 iteratively by the predetermined number of times, for example, several or scores of times to output the decoded data D213 on the basis of the extrinsic information of soft-output obtained as a result of the predetermined number of times of the decoding operation.
Incidentally, the coding apparatus 201 has a problem, since there are many bits need be processed in various parts, of bringing forth complicatedness of constitution of various parts and making a circuit scale huge. Further, the decoding apparatus 203 is also complicated in constitution of various parts with the complicatedness of the coding apparatus 201. For solving this problem, there have been proposed a coding apparatus 401 shown in FIGS. 7 and 9, and a decoding apparatus 403 shown in FIG. 10. The coding apparatus 401 and the decoding apparatus 403 will be described hereinafter. Needless to say, the coding apparatus 401 and the decoding apparatus 403 take the place of the coding apparatus 201 and the decoding apparatus 203 in the communication model shown in FIG. 1 previously.
The coding apparatus 401 comprises, as shown in FIG. 7, a convolutional coder 410 for carrying out coding of outer codes, an interleaver 420 for rearranging order of data input, a convolutional coder 430 for carrying out coding of inner codes, and a multi-value modulation mapping circuit 440 for carrying out mapping of signal points base on the predetermined modulation system. The coding apparatus 401 carries out serially concatenated convolutional operation whose code rate is “2/3” with respect to the input data D401 of 2 bits input to convert it into coded data D404 of 3 bits, and applies mapping to a transmission symbol of the 8 PSK modulation system, for example, to output it as one coded transmission symbol D405 of 3 bits.
The convolutional coder 410 comprises, as shown in FIG. 8, three exclusive OR circuits 411, 413, 415, and two shift registers 412, 414.
The exclusive OR circuit 411 uses input data D4011, 4012 of 2 bits to carry out exclusive OR operation and supplies the operation result to the shift register 412.
The shift register 412 continues to supply data of 1 bit being held to the exclusive OR circuit 413. The shift register 412 is synchronized with a clock to newly hold data of 1 bit supplied from the exclusive OR circuit 411, and newly supplies that data to the exclusive OR circuit 413.
The exclusive OR circuit 413 uses data supplied from the shift register 412 and input data D4011 of 1 bit out of input data D401 of 2 bits to carry out exclusive OR operation to supply the operation result to the shift register 414.
The shift register 414 continues to supply data of 1 bit being held to the exclusive OR circuit 415. The shift register 414 is synchronized with a clock to newly hold data of 1 bit supplied from the exclusive OR circuit 413, and newly supplies that data to the exclusive OR circuit 415.
The exclusive OR circuit 415 uses data supplied from the shift register 414 and input data D4011, D4012 to carry out exclusive OR operation to supply the operation result to the interleaver 420 in the later stage as coded data D4023 of 1 bit out of coded data D402 of 3 bits.
The convolutional coder 410 as described carries out, when input data D4011 and D4012 are input, convolutional operation with respect to these input data D4011 and D4012 to output the operation result tot he interleaver 420 in the later stage as coded data D4021, D4022, D4023. That is, the convolutional coder 410 carries out convolutional operation whose code rate is “2/3” as coding of outer codes and outputs coded data D402 to the interleaver 420 in the later stage.
The interleaver 420 has the constitution similar to that of the interleaver 220 shown in FIG. 4 previously, and the size thereof is reduced to be smaller than the interleaver 220. That is, the interleaver 420 is reduced in circuit scale as compared with the interleaver 220 since input/output of 3 bits is carried out in place of input/output of 5 bits. The interleaver 420 inputs coded data D402 comprising three bit series output from the convolutional coder 410, and rearranges order of bits constituting the coded data D402 on the basis of exchange position information stored in advance to produce the interleave data D403.
The convolutional coder 430 comprises, as shown in FIG. 9, an exclusive OR circuit 431 and a shift register 432.
The exclusive OR circuit 431 uses interleave data D4031, D4032, D4033 to carry out exclusive OR operation to output the operation result to the multi-value modulation mapping circuit 440 in the later stage as coded data D4043 of 1 bit out of coded data D404 of 3 bits and supply it to the shift register 432.
The shift register 432 continues to supply data of 1 bit being held to the exclusive OR circuit 431. The shift register 432 is synchronized with a clock to newly hold data of 1 bit supplied from the exclusive OR circuit 431, and newly supplies that data to the exclusive OR circuit 431.
The convolutional coder 430 carries out, when the interleave data D4031, D4032, D4033 are input, convolutional operation with respect to these interleave data D4031, D4032, D4033 to output the operation result to the multi-value modulation mapping circuit 440 as coded data D4041, D4042, D4043 of 3 bits. That is, the convolutional coder 430 carries out convolutional operation whose code rate is “3/3=1” as coding of inner codes to output coded data D404 to the multi-value mapping circuit 440.
The multi-value mapping circuit 440 causes coded data D404 output from the convolutional coder 430 to synchronize with a clock to apply mapping thereto to a transmission symbol of the 8 PSK modulation system, for example. The multi-value mapping circuit 440 carries out mapping with respect to coded data D404 of 3 bits output from the convolutional coder 430 as one transmission symbol to produce one coded transmission symbol D405. The multi-value mapping circuit 440 outputs the produced coded transmission symbol D405 to the outside.
The coding apparatus 401 as described carries out convolutional operation whose code rate is “2/3” as coding of outer codes by the convolutional coder 410, and convolutional operation whose code rate is “1” as coding of inner codes is carried out by the convolutional coder 430, whereby carrying out serially concatenated convolutional operation whose code rate is “(2/3)×1=2/3” as a whole. That is, the coding apparatus 401 is able to hold the code rate as the same “2/3” despite the simple constitution as compared with the coding apparatus 201 since the number of bits need be processed in various parts will suffice to be small. Data coded and modulated by the coding apparatus 401 are output to the receiving apparatus through the memoryless channel 202.
On the other hand, the decoding apparatus 403 comprises, as shown in FIG. 10, a soft-output decoding circuit 450 for carrying out decoding of inner codes, a deinterleaver 460 for returning order of data input to the original state, an interleaver 470 for rearranging order of data input, and a soft-output decoding circuit 480 for carrying out decoding of outer codes. The decoding apparatus 403 presumes input data D401 in the coding apparatus 401 from a reception word D406 which takes an analog value and which is to be a soft-input due to the influence of noises generated on the memoryless channel 202 to output it as decoded data D411.
The soft-output decoding circuit 450 is provided corresponding to the convolutional coder 410 in the coding apparatus 40, and carries out MAP decoding on the basis of the aforementioned BCJR algorithm or SOVA decoding. The soft-output decoding circuit 450 inputs a reception word D406 received by the receiving apparatus inputs priori probability information D407 with respect to the information bit of soft-input supplied from the interleaver 470, and uses these reception word D406 and priori probability information D407 to carry out soft-output decoding of inner codes. The soft-output decoding circuit 450 produces extrinsic information D408 with respect to the information bit obtained according to the constraint condition of codes to output the extrinsic information D408 to the interleaver 460 in the later stage as a soft-output. The extrinsic information D408 corresponds to the interleave data D403 interleaved by the interleaver 420 in the coding apparatus 401.
The deinterleaver 460 applies the deinterleave to the extrinsic information D408 of soft-input output from the soft-output decoding circuit 450 so that the bit array of the interleave data D403 interleaved by the interleaver 420 in the coding apparatus 401 is returned to the original bit array of the coded data D402. The deinterleaver 460 outputs data obtained by deinterleaving as priori probability information D409 with respect to the coded bit in the soft-output decoding circuit 480 in the later stage.
The interleaver 470 applies the interleave base on the same exchange position information as the interleaver 420 in the coding apparatus 401 with respect to the extrinsic information D410 with respect to the code bit which is output from the soft-output decoding circuit 480 and which is to be a soft-input. The interleaver 470 outputs data obtained by interleaving as priori probability information D407 with respect to the information bit in the soft-output decoding circuit 450.
The soft-output decoding circuit 480 is provided corresponding to the convolutional coder 419 in the coding apparatus 401, and carries out MAP decoding based on the aforementioned BCRJ algorithm or SOVA decoding similar to the soft-output decoding circuit 450. The soft-output decoding circuit 480 inputs priori probability information D409 with respect to the code bit of soft-input output from the deinterleaver 460, inputs priori probability information with respect to the information bit whose value is “0”, though not shown, and uses these priori probability information to carry out soft-output decoding of outer codes. The soft-output decoding circuit 480 produces extrinsic information D410 with respect to the code bit obtained according to the constraint condition of codes, and outputs the extrinsic information D410 to the interleaver 470 as a soft-output. Further, The soft-output decoding circuit 480 produces extrinsic information with respect to the information bit obtained according to the constraint condition of codes, and outputs decoded data D411 on the basis of the extrinsic information though not shown.
The decoding apparatus 403 as described carries out, when the reception word D406 is received, decoding operation from the soft-output decoding circuit 450 to the soft-output decoding circuit 480 iteratively by the predetermined number of times, for example, several or scores of times to output the decoded data D411 on the basis of the extrinsic information of soft-output obtained as a result of the predetermined number of times of the decoding operation. That is, the decoding apparatus 403 is able to carry out decoding of the received reception word D406 with the simple constitution as compared with the decoding apparatus 203 since the number of bits of input/output with respect to various parts is small.
As described above, the system composed of the coding apparatus 401 and the decoding apparatus 403 is reduced in circuit scale of various parts as compared with the system composed of the coding apparatus 201 and the decoding apparatus 203.
As described above, the system composed of the coding apparatus 401 and the decoding apparatus 403 is able to carry out error correction coding and decoding rate as compared with the system composed of the coding apparatus 201 and the decoding apparatus 203, but poses a problem that the performance is somewhat poor.
For the purpose of explaining concretely, FIG. 11 shows the performance curve given by a relationship between an logarithm expression (log10BER) and a signal/noise power ratio (Eb/No) per 1 bit. In the figure, both the multi-value mapping circuit 240 in the coding apparatus 201 and the multi-value mapping circuit 440 in the coding apparatus 401 carry out mapping with respect to signal points, and makes the input distance sum of the minimum Euclidean distance “16”, as shown in FIG. 12.
As will be apparent from FIG. 11, it is understood that the performance curve in the system composed of the coding apparatus 201 and the decoding apparatus 203 presents the so-called water fall phenomenon in the range from about 3 dB to about 3.5 dB relative to Eb/No, and presents the so-called error floor phenomenon in the range of about 3.5 dB or more relative to Eb/No. On the other hand, it is understood that the performance curve in the system composed of the coding apparatus 401 and the decoding apparatus 403 will be a water fall region in the high range of about 0.3 dB relative to Eb/No as compared with the performance curve in the system composed of the coding apparatus 201 and the decoding apparatus 203. This indicates that the system composed of the coding apparatus 201 and the decoding apparatus 203 has the coded gain of about 0.3 dB as compared with the system composed of the coding apparatus 401 and the decoding apparatus 403. It is understood therefrom that the system composed of the coding apparatus 401 and the decoding apparatus 403 is lower in the performance than the system composed of the coding apparatus 201 and the decoding apparatus 203, and actually there still remains room m for improvement.